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1 ? hd-6409 cmos manchester encoder-decoder the hd-6409 manchester encoder-decoder (med) is a high speed, low power device manufactured using self-aligned silicon gate technology. the devi ce is intended for use in serial data communication, and can be operated in either of two modes. in the converter mode, the med converts non return-to-zero code (nrz) into manchester code and decodes manchester code into nonreturn-to-zero code. for serial data communication, manchester code does not have some of the deficiencies inhere nt in nonreturn-to-zero code. for instance, use of the med on a serial line eliminates dc components, provides clock recovery, and gives a relatively high degree of noise immunity. because the med converts the most commonly used code (nrz) to manchester code, the advantages of using manchester code are easily realized in a serial data link. in the repeater mode, the med accepts manchester code input and reconstructs it with a recovered clock. this minimizes the effects of noise on a serial data link. a digital phase lock loop generates the recovered clock. a maximum data rate of 1mhz requires only 50mw of power. manchester code is used in magnetic tape recording and in fiber optic communication, and generally is used where data accuracy is imperative. because it frames blocks of data, the hd-6409 easily interfaces to protocol controllers. features ? converter or repeater mode ? independent manchester encoder and decoder operation ? static to one megabit/sec data rate guaranteed ? low bit error rate ? digital pll clock recovery ? on chip oscillator ? low operating power: 50mw typical at +5v ? pb-free available (rohs compliant) pinout hd-6409 (20 ld pdip, soic) top view 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 bzi boi udi sd/cds sdo srst dclk nvm rst gnd v cc bzo ss eclk boo cts ms o x i x co ordering information part number (1 megabit/sec) part marking temp. range (c) package pkg. dwg. # hd3-6409-9 hd3-6409-9 -40 to +85 20 ld pdip e20.3 HD3-6409-9Z (notes 2, 3) HD3-6409-9Z -40 to +85 20 ld pdip (pb-free) e20.3 hd9p6409-9 hd9p6409-9 -40 to +85 20 ld soic m20.3 hd9p6409-9z (notes 2, 3) hd9p6409-9z -40 to +85 20 ld soic (pb-free) m20.3 hd9p6409-9z96 (notes 1, 2, 3) hd9p6409-9z -40 to +85 20 ld soic tape & reel (pb-free) m20.3 notes: 1. ?96? suffix is for tape and reel. please refe r to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged pr oducts employ special pb-free material se ts, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination fi nish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classifi ed at pb-free peak reflow temperatures that meet or exceed the pb-free requirements o f ipc/jedec j std-020. 3. pb-free pdips can be used for through hole wave solder processi ng only. they are not intended for use in reflow solder proces sing applications. fn2951.3 data sheet october 15, 2008 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 1997, 2005, 2008. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn2951.3 october 15, 2008 block diagram logic symbol edge detector command sync generator output select logic boi bzi udi rst sd/cds i x o x co ss reset 5-bit shift register and decoder data input logic input/ output select oscillator counter circuits manchester encoder sdo nvm boo bzo cts srst ms eclk dclk sd clock generator encoder control decoder ss co sd/cds eclk ms rst sdo dclk nvm srst o x i x boo bzo cts boi bzi udi 13 12 19 18 15 2 1 3 17 11 4 16 14 8 7 6 5 9 hd-6409 hd-6409
3 fn2951.3 october 15, 2008 pin descriptions pin number type symbol name description 1 i bzl bipolar zero input used in conjunction with pin 2, bipolar one input (bol), to input manchester ii encoded data to the decoder, bzi and bol are logical co mplements. when using pin 3, unipolar data input (udi) for data input, bzi must be held high. 2 i bol bipolar one input used in conjunct ion with pin 1, bipolar zero input (bzi), to input manchester ii encoded data to the decoder, boi and bzi are logical complements. when using pin 3, unipolar data input (udi) for data input, bol must be held low. 3 i udi unipolar data input an alternate to bipolar input (b zl, bol), unipolar data input (udl) is used to input manchester ii encoded data to the decoder. w hen using pin 1 (bzl) and pin 2 (bol) for data input, udi must be held low. 4 i/o sd/cds serial data/command data sync in the converter mode, sd/cds is an input us ed to receive serial nrz data. nrz data is accepted synchronously on the falling edge of encoder clock output (eclk). in the repeater mode, sd/cds is an output indicating the status of last valid sync pattern received. a high indicates a command sync and a low indicates a data sync pattern. 5 o sdo serial data out the decoded serial nrz data is tr ansmitted out synchronously with the decoder clock (dclk). sdo is forced low when rst is low. 6 o srst serial reset in the converter mode, srst follows rst . in the repeater mode, when rst goes low, srst goes low and remains low after rst goes high. srst goes high only when rst is high, the reset bit is zero, and a va lid synchronization sequence is received. 7onvm nonvalid manchester a low on nvm indicates that the decoder has received invalid manchester data and present data on serial data out (sdo) is invalid. a high indicates that the sync pulse and data were valid and sdo is valid. nvm is set low by a low on rst , and remains low after rst goes high until valid sync pulse followed by two valid manchester bits is received. 8 o dclk decoder clock the decoder clock is a 1x clock reco vered from bzl and bol, or udi to synchronously output received nrz data (sdo). 9irst reset in the converter mode, a low on rst forces sdo, dclk, nvm , and srst low. a high on rst enables sdo and dclk, and forces srst high. nvm remains low after rst goes high until a valid sync pulse fo llowed by two manchester bits is received, after which it goes high. in the repeater mode, rst has the same effect on sdo, dclk and nvm as in the converter mode. when rst goes low, srst goes low and remains low after rst goes high. srst goes high only when rst is high, the reset bit is zero and a valid synchronization sequence is received. 10 i gnd ground ground 11 o c o clock output buffered output of clock input i x . may be used as clock signal for other peripherals. 12 i i x clock input i x is the input for an external clock or, if the internal oscillator is used, i x and o x are used for the connection of the crystal. 13 o o x clock drive if the internal oscillator is used, o x and i x are used for the connection of the crystal. 14 i ms mode select ms must be held low for operation in the converter mode, and high for operation in the repeater mode. 15 i cts clear to send in the converter mode, a high disables the encoder, forcing outputs boo , bzo high and eclk low. a high to low transition of cts initiates transmission of a command sync pulse. a low on cts enables boo , bzo , and eclk. in the repeater mode, the function of cts is identical to that of the converter mode with the exception that a transition of cts does not initiate a synchronization sequence. 16 o eclk encoder clock in the converter mode, eclk is a 1x clock output used to receive serial nrz data to sd/cds. in the repeater mode, eclk is a 2x clock which is recovered from bzl and bol data by the digital phase locked loop. 17 i ss speed select a logic high on ss sets the data rate at 1/32 times the clock frequency while a low sets the data rate at 1/16 times the clock frequency. 18 o bzo bipolar zero output bzo and its logical complement boo are the manchester data outputs of the encoder. the inactive state for these outputs is in the high state. 19 o boo bipolar one out see pin 18. 20 i v cc v cc v cc is the +5v power supply pin. a 0.1f decoupling capacitor from v cc (pin 20) to gnd (pin 10) is recommended. note: (i) input (o) output hd-6409 hd-6409
4 fn2951.3 october 15, 2008 encoder operation the encoder uses free running clocks at 1x and 2x the data rate derived from the system clock l x for internal timing. cts is used to control the enc oder outputs, eclk, boo and bzo . a free running 1x eclk is transmitted out of the encoder to drive the external circuits which supply the nrz data to the med at pin sd/cds. a low on cts enables encoder outputs eclk, boo and bzo , while a high on cts forces bzo , boo high and holds eclk low. when cts goes from high to low , a synchronization sequence is transmitted out on boo and bzo . a synchronization sequence consists of eight manchester ?0? bits followed by a command sync pulse. a command sync pulse is a 3-bit wide pulse with the first 1 1/2 bits high followed by 1 1/2 bits low. serial nrz data is clocked into the encoder at sd/cds on the high to low transition of eclk during the command sync pulse. the nrz data received is encoded into manchester ii data and transmitted out on boo and bzo following the command sync pulse. following the synchronization sequence, input data is encoded and transmitted out continuously without parity check or word fr aming. the length of the data block encoded is defined by cts . manchester data out is inverted. decoder operation the decoder requires a single clock with a frequency 16x or 32x the desired data rate. the rate is selected on the speed select with ss low producing a 16x clock and high a 32x clock. for long data links the 32x mode should be used as this permits a wider timing jitter margin. the internal operation of the decoder utilizes a free running clock synchronized with incoming data for its clocking. the manchester ii encoded data can be presented to the decoder in either of two ways. the bipolar one and bipolar zero inputs will accept data from differential inputs such as a comparator sensed transformer coupled bus. the unipolar data input can only accept noninverted manchester ii encoded data i.e. bipolar one out through an inverter to unipolar data input. the decoder continuously monitors this data input for valid sync patt ern. note that while the med encoder section can generate only a command sync pattern, the decoder can recognize either a command or data sync pattern. a data sync is a logi cally inverted command sync. there is a three bit delay between udi, bol, or bzi input and the decoded nrz data transmitted out of sdo. control of the decoder outputs is provided by the rst pin. when rst is low, sdo, dclk and nvm are forced low. when rst is high, sdo is transmitted out synchronously with the recovered clock dclk. the nvm output remains low after a low to high transition on rst until a valid sync pattern is received. the decoded data at sdo is in nrz format. dclk is provided so that the decoded bits can be shifted into an external register on every high to low transition of this clock. three bit periods after an invalid manchester bit is received on udi, or bol, nvm goes low synchronously with the questionable data output on sdo. further, the decoder does not re-establish proper data decoding until another sync pattern is recognized. 1 2 3 4 cts eclk sd/cds bzo boo t ce6 0 000 00 00 t ce5 synchronization sequence eight ?0?s? command sync don?t care ?1? ?0? ?1? ?1? ?0? ?1? figure 1. encoder operation 1 2 3 4 hd-6409 hd-6409
5 fn2951.3 october 15, 2008 repeater operation manchester il data can be pres ented to the repeater in either of two ways. the inputs bipolar one in and bipolar zero in will accept data from differential inputs such as a comparator or sensed transformer coupled bus. the input unipolar data in accepts only noninverted m anchester ii coded data. the decoder requires a single clock with a frequency 16x or 32x the desired data rate. this clock is selected to 16x with speed select low and 32x with speed select high. for long data links the 32x mode should be used as this permits a wider timing jitter margin. the inputs udl, or bol, bzl are delayed approximately 1/2 bit period and repeated as outputs boo and bzo . the 2x eclk is transmitted out of th e repeater synchronously with boo and bzo . a low on cts enables eclk, boo , and bzo . in contrast to the converter mode, a transiti on on cts does not initiate a synchronization sequence of eight 0?s and a command sync. the repeater mode does recognize a command or data sync pulse. sd/cds is an output whic h reflects the state of the most recent sync pulse received, with high indicating a command sync and low indicating a data sync. when rst is low, the outputs sdo, dclk, and nvm are low, and srst is set low. srst remains low after rst goes high and is not reset until a sync pulse and two valid manchester bits are received with the reset bit low. the reset bit is the first data bit after the sync pulse. with rst high, nrz data is transmitted out of serial data out synchronously with the 1x dclk. figure 2. decoder operation dclk udi sdo rst nvm command sync 1001010101010 figure 3. repeater operation input count eclk udi bzo boo rst srst sync pulse 12 3 4567 hd-6409 hd-6409
6 fn2951.3 october 15, 2008 manchester code nonreturn-to-zero (nrz) code represents the binary values logic-o and iogic-1 with a static level maintained throughout the data cell. in contrast, manchester code represents data with a level transition in the middle of the data cell. manchester has bandwidth, error detection, and synchronization advantages over nrz code. the manchester ii code bipolar one and bipolar zero shown below are logical complements. the direction of the transition indicates the binary value of data. a logic-0 in bipolar one is defined as a low to high transition in the middle of the data cell, and a logic-1 as a high to low mid bit transition, manchester il is also known as biphase-l code. the bandwidth of nrz is from dc to the clock frequency fc/2, while that of manchester is from fc/2 to fc. thus, manchester can be ac or transformer coup led, which has considerable advantages over dc coupling. also, the ratio of maximum to minimum frequency of manchester extends one octave, while the ratio for nrz is the range of 5 to 10 octaves. it is much easier to design a narrow band than a wideband amp. secondly, the mid bit transition in each data cell provides the code with an effective error detection scheme. if noise produces a logic inversion in the data cell such that there is no transition, an error indiction is given, and synchronization must be re-established. this places relatively stringent requirements on the incoming data. the synchronization advantages of using the hd-6409 and manchester code are several fold . one is that manchester is a self clocking code. the clock in serial data communication defines the position of each data cell. non self clocking codes, as nrz, often require an extra clock wire or clock track (in magnetic recording). further, there can be a phase variation between the clock and data track. crosstalk between the two may be a problem. in manchester, the serial data stream contains both the clock and the data, with the position of the mid bit transition representing the clock, and the direction of the transit ion representing data. there is no phase variation between the clock and the data. a second synchronization advantage is a result of the number of transitions in the data. the decoder resynchronizes on each transition, or at least once every data cell. in contrast, receivers using nrz, which does not necessarily have transitions, mu st resynchronize on frame bit transitions, which occur far less often, usually on a character basis. this more frequent resynchronization eliminates the cumulative effe ct of errors over successive data cells. a final synchronization advantage concerns the hd-6409?s sync pulse used to initiate synchronization. this three bit wide pattern is sufficiently distinct from manchester data that a false start by the receiver is unlikely. figure 4. manchester code bit period binary code nonreturn to zero bipolar one bipolar zero 123 45 011 00 crystal oscillator mode figure 5. crystal oscillator mode lc oscillator mode figure 6. lc oscillator mode i x o x x1 r1 c0 16mhz c1 c1 c o c1 = 32pf c0 = crystal + stray x1 = at cut parallel resonance fundamental mode r s (typ) = 30 r1 = 15m c1 c1 l c e c1 2c0 ? 2 ------------------------- - f o 1 2 lc e ----------------------- c1 = 20pf c0 = 5pf i x o x hd-6409 hd-6409
7 fn2951.3 october 15, 2008 using the 6409 as a ma nchester encoded uart v cc boo bzo ss eclk cts ms o x i x co bzi boi udi sd/cds sdo srst nvm dclk rst gnd bipolar out bipolar out cts load load qh ck si ?165 load qh ck ?165 b qh a ?164 b ck a ?164 ck data in ?273 data in ?273 cp reset bipolar in bipolar in figure 7. manchester encoder uart parallel data out parallel data in hd-6409 hd-6409
8 fn2951.3 october 15, 2008 common electrical specifications parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits established by char acterization and are not production tested. absolute maximum rati ngs thermal information supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0v input, output or i/o voltage . . . . . . . . . . . . gnd -0.5v to v cc +0.5v esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 operating conditions operating temperature range . . . . . . . . . . . . . . . . .-40c to +85c operating voltage range. . . . . . . . . . . . . . . . . . . . . . +4.5v to +5.5v input rise and fall times . . . . . . . . . . . . . . . . . . . . . . . . . 50ns max sync. transition span (t2) . . . . . . . . . .1.5 dbp typical, (notes 1, 2) short data transition span (t4) . . . . . . 0.5dbp typical, (notes 1, 2) long data transition span (t5) . . . . . . 1.0dbp typical, (notes 1, 2) zero crossing tolerance (tcd5) . . . . . . . . . . . . . . . . . . . . . (note 3) thermal resistance (typical, note 4) ja (c/w) jc (c/w) pdip package . . . . . . . . . . . . . . . . . . . 75 n/a soic package . . . . . . . . . . . . . . . . . . . 100 n/a storage temperature range . . . . . . . . . . . . . . . . . .-65c to +150c maximum junction temperature ceramic package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175c plastic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp *pb-free pdips can be used for through hole wave solder processing only. they are not intended for use in reflow solder processing applications. die characteristics gate count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250 gates caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. dbp-data bit period, clock rate = 16x, one dbp = 16 clo ck cycles; clock rate = 32x, one dbp = 32 clock cycles. 2. the input conditions specif ied are nominal values, the actual input waveforms transition spans may vary by 2 i x clock cycles (16x mode) or 6 i x clock cycles (32x mode). 3. the maximum zero crossing tolerance is 2 i x clock cycles (16x mode) or 6 i x clock cycles (32 mode) from the nominal. 4. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. dc electrical specifications v cc = 5.0v 10%, t a = -40 c to +85 c (hd-6409-9). symbol parameter test conditions (note 5) min max units v ih logical ?1? input voltage v cc = 4.5v 70% v cc -v v il logical ?0? input voltage v cc = 4.5v - 20% v cc v v ihr logic ?1? input voltage (reset )v cc = 5.5v v cc -0.5 - v v ilr logic ?0? input voltage (reset )v cc = 4.5v - gnd +0.5 v v ihc logical ?1? input voltage (clock) v cc = 5.5v v cc -0.5 - v v ilc logical ?0? input voltage (clock) v cc = 4.5v - gnd +0.5 v i i input leakage current (except i x )v in = v cc or gnd, v cc = 5.5v -1.0 +1.0 a i i input leakage current (i x )v in = v cc or gnd, v cc = 5.5v -20 +20 a i o i/o leakage current v out = v cc or gnd, v cc = 5.5v -10 +10 a v oh output high voltage (all except o x )i oh = -2.0ma, v cc = 4.5v (note 6) v cc -0.4 - v v ol output low voltage (all except o x )i ol = +2.0ma, v cc = 4.5v (note 6) - 0.4 v i ccsb standby power supply current v in = v cc or gnd, v cc = 5.5v, outputs open - 100 a i ccop operating power supply current f = 16.0mhz, v in = v cc or gnd v cc = 5.5v, c l = 50pf - 18.0 ma f t functional test (note 5) - - - notes: 5. tested as follows: f = 16mhz, v ih = 70% v cc , v il = 20% v cc , v oh v cc /2, and v ol v cc /2, v cc = 4.5v and 5.5v. 6. interchanging of force and s ense conditions is permitted hd-6409 hd-6409
9 fn2951.3 october 15, 2008 capacitance t a = +25c, frequency = 1mhz. symbol parameter test conditions typ units c in input capacitance all measurements are referenced to device gnd 10 pf c out output capacitance 12 pf ac electrical specifications v cc = 5.0v 10%, t a = -40c to +85c (hd-6409-9). symbol parameter test conditions (note 7) min max units f c clock frequency - - 16 mhz t c clock period - 1/f c -sec t 1 bipolar pulse width - t c +10 - ns t 3 one-zero overlap - - t c -10 ns t ch clock high time f = 16.0mhz 20 - ns t cl clock low time f = 16.0mhz 20 - ns t ce1 serial data setup time - 120 - ns t ce2 serial data hold time - 0 - ns t cd2 dclk to sdo, nvm - - 40 ns t r2 eclk to bzo - - 40 ns t r output rise time (all except clock) from 1.0v to 3.5v, c l = 50pf, note 8 - 50 ns t f output fall time (all except clock) from 3.5v to 1.0v, c l = 50pf, note 8 - 50 ns t r clock output rise time from 1.0v to 3.5v, c l = 20pf, note 8 - 11 ns t f clock output fall time from 3.5v to 1.0v, c l = 20pf, note 8 - 11 ns t ce3 eclk to bzo , boo notes 8, 9 0.5 1.0 dbp t ce4 cts low to bzo , boo enabled notes 8, 9 0.5 1.5 dbp t ce5 cts low to eclk enabled notes 8, 9 10.5 11.5 dbp t ce6 cts high to eclk disabled notes 8, 9 - 1.0 dbp t ce7 cts high to bzo , boo disabled notes 8, 9 1.5 2.5 dbp t cd1 udi to sdo, nvm notes 8, 9 2.5 3.0 dbp t cd3 rst low to cdlk, sdo, nvm low notes 8, 9 0.5 1.5 dbp t cd4 rst high to dclk, enabled notes 8, 9 0.5 1.5 dbp t r1 udi to bzo , boo notes 8, 9 0.5 1.0 dbp t r3 udi to sdo, nvm notes 8, 9 2.5 3.0 dbp notes: 7. ac testing as follows: f = 4.0mhz, v ih = 70% v cc , v il = 20% v cc , speed select = 16x, v oh v cc /2, v ol v cc /2, v cc = 4.5v and 5.5v. input rise and fall times driven at 1ns/v, output load = 50pf. 8. limits established by characte rization and are not production tested. 9. dbp-data bit period, clock rate = 16x, one dbp = 16 cl ock cycles; clock rate = 32x, one dbp = 32 clock cycles. hd-6409 hd-6409
10 fn2951.3 october 15, 2008 timing waveforms figure 8. figure 9. clock timing figure 10. output waveform data sync bit period bit period bit period t 2 command sync t 2 t 3 t 3 t 2 t 2 t 4 one one zero t 1 t 1 t 1 t 3 t 3 t 1 t 1 t 1 t 3 t 3 t 3 t 3 t 1 t 4 t 5 t 5 t 2 t 2 command sync t 2 t 2 t 4 t 5 t 5 t 4 t 4 zero one one one data sync boi bzi boi bzi boi bzi udi udi udi t 3 note: udi = 0, for next diagrams note: boi = 0, bzi = 1 for next diagrams t c t ch t r t cl t f 10% 90% t r t f 1.0v 3.5v hd-6409 hd-6409
11 fn2951.3 october 15, 2008 figure 11. encoder timing figure 12. encoder timing figure 13. encoder timing note: manchester data-in is not synchronous with decoder clock. decoder clock is synchronous with decoded nrz out of sdo. figure 14. decoder timing figure 15. decoder timing figure 16. decoder timing timing waveforms (continued) eclk sd/cds bzo boo t ce1 t ce2 t ce3 t ce5 t ce4 cts bzo boo eclk t ce6 cts bzo boo eclk t ce7 dclk udi sdo nvm manchester logic-1 manchester logic-0 manchester logic-0 manchester logic-1 t cd2 t cd5 t cd2 t cd1 nrz logic-1 rst dclk, sdo, nvm 50% 50% t cd3 rst dclk 50% t cd4 hd-6409 hd-6409
12 fn2951.3 october 15, 2008 test load circuit figure 17. repeater timing timing waveforms (continued) udi eclk bzo sdo nvm manchester ?1? t r2 t r3 t r3 t r2 t r1 manchester ?0? manchester ?0? manchester ?1? manchester ?1? manchester ?0? manchester ?0? figure 18. test load circuit dut c l (note) note: includes stray and jig capacitance hd-6409 hd-6409
13 fn2951.3 october 15, 2008 hd-6409 dual-in-line plastic packages (pdip) notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the inch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the ?mo series symbol list? in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are measured with the package seated in jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shal l not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be perpen- dicular to datum . 7. e b and e c are measured at the lead tips with the leads uncon- strained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dam- bar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a1 -a- 0.010 (0.25) c a m bs e20.3 (jedec ms-001-ad issue d) 20 lead dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.210 - 5.33 4 a1 0.015 - 0.39 - 4 a2 0.115 0.195 2.93 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.045 0.070 1.55 1.77 8 c 0.008 0.014 0.204 0.355 - d 0.980 1.060 24.89 26.9 5 d1 0.005 - 0.13 - 5 e 0.300 0.325 7.62 8.25 6 e1 0.240 0.280 6.10 7.11 5 e 0.100 bsc 2.54 bsc - e a 0.300 bsc 7.62 bsc 6 e b - 0.430 - 10.92 7 l 0.115 0.150 2.93 3.81 4 n20 209 rev. 0 12/93
14 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn2951.3 october 15, 2008 hd-6409 small outline plast ic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m b s e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m m20.3 (jedec ms-013-ac issue c) 20 lead wide body small outline plastic package symbol inches millimeters notes min max min max a 0.0926 0.1043 2.35 2.65 - a1 0.0040 0.0118 0.10 0.30 - b 0.014 0.019 0.35 0.49 9 c 0.0091 0.0125 0.23 0.32 - d 0.4961 0.5118 12.60 13.00 3 e 0.2914 0.2992 7.40 7.60 4 e 0.050 bsc 1.27 bsc - h 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 l 0.016 0.050 0.40 1.27 6 n20 207 0 8 0 8 - rev. 2 6/05

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